Verilog Skill For Claude

Verilog Skill for Claude

🚀 Overview

This repository provides a **Verilog HDL skill module** designed to augment Claude AI for **RTL design, code generation, debugging, and verification workflows**.

The focus of this project is not just learning — but enabling **engineer-level productivity** in digital design by integrating structured Verilog knowledge with AI-assisted workflows.

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🎯 Purpose

Modern RTL design requires speed, accuracy, and strong debugging capability. This project is built to:

• Accelerate RTL development cycles
• Assist in writing synthesizable and clean Verilog code
• Improve debugging efficiency
• Provide design-aware responses instead of generic AI outputs
• Support real-world VLSI workflows

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⚙️ Core Capabilities

🔧 RTL Design Assistance

• Parameterized module generation
• Combinational and sequential logic design
• FSM implementation
• Synthesizable coding practices

🐞 Debugging & Code Review

• Detection of:

  • Race conditions
  • Latch inference
  • Blocking vs non-blocking issues
  • Simulation vs synthesis mismatches

• Root-cause analysis with fixes

🧪 Verification Support

• Testbench development
• Simulation constructs and debugging
• Functional validation strategies

📐 Synthesis-Aware Coding

• Ensures generated code aligns with synthesis constraints
• Avoids non-synthesizable constructs
• Highlights hardware implications

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🧠 Design Approach

The skill is built with a **design-first mindset**, ensuring:

• All outputs are hardware-relevant
• Emphasis on RTL correctness over syntax
• Awareness of toolchain behavior (simulation vs synthesis)
• Alignment with industry coding standards

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📂 Repository Structure

Verilog-Skill-for-Claude/
│
├── Skill.md                # Core AI skill definition
│
├── references/             # Domain knowledge base
│   ├── 01_lexical_and_datatypes.md
│   ├── 02_modules_and_hierarchy.md
│   ├── 03_b