ChengminLi

AI PCB Layout — AI skill for Claude Code

AI community

AI agent skill for designing and reviewing power-electronics PCBs, with a human review gate after every step.

How to install AI PCB Layout

This entry records only its repository, not the path inside it, so there is no exact command to give. Open ChengminLi/AI-PCB-layout and copy the folder into ~/.claude/skills/, or the file into ~/.claude/agents/.

What AI PCB Layout does

AI agent skill for designing and reviewing power-electronics PCBs, with a human review gate after every step.

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README

AI PCB Layout

[![License: CC BY 4.0](https://img.shields.io/badge/License-CC_BY_4.0-lightgrey.svg)](https://creativecommons.org/licenses/by/4.0/) A gift for hardware engineer.

An AI agent skill for **designing, reviewing, and improving power-electronics PCBs**. This skill does not produce a PCB at the first try, instead it provides a way of how to collobrate with the AI agents to boost the productivity of PCB layout. I expect that the user has at least midlevel hardware experience, thus can provide engineering judgement to review the results.

The skill teaches an AI coding agent (Cursor, Claude Code, Codex, or any agent that supports `SKILL.md` skills) to work like a careful power-electronics layout engineer: it traces commutation and gate loops from the switching states, derives clearance and copper limits from standards and design currents, and **stops for your approval after every step**, so you stay in control of every design decision.

**Note:** The skill helps you reach a well-reasoned design and tells you which evidence is still missing. It does not certify safety or EMC compliance. Measurements and the applicable standards remain the final authority.

What it covers

  • Electrical net table: worst-case peak voltage, dv/dt, RMS current, and di/dt for each key node and current path, taken from simulation or calculation, and turned into layout constraints
  • Switching loops: commutation cells, gate charge and discharge loops, Kelvin connections, and common-mode paths, derived per switching transition
  • Insulation: clearance, creepage, and solid insulation derived from the applicable standard and its inputs, never copied from example values
  • Copper capability: conductor and via sizing from worst-case RMS current and permitted temperature rise
  • Placement and routing: functional block floorplans, routability checks, and a routing plan you approve before any copper is drawn
  • Verification: DRC, insulation geometry, parasitic ext