Verilog Generator

verilog-generator

A Claude Code skill that generates single, synthesizable Verilog modules from natural language descriptions or interface definitions.

Features

• Natural language to RTL — describe the module in plain text, get a complete Verilog implementation
• Verilog-2005 strict mode — enforces pre-SystemVerilog syntax, no logic, always_ff, or interface
• Full AXI protocol support — correct handshake validation for AXI-Stream, AXI4-Lite, and AXI4-Full
• 14-point self-check pipeline — every generated module passes a comprehensive checklist before output
• Customizable coding style — supply a Markdown rule file and/or a Verilog template to override defaults

File Structure

verilog-generator/
├── SKILL.md          # Skill definition: mandatory rules, workflow, output format
├── coding_style.md   # Built-in coding style guide (27 sections, lowRISC adapted for Verilog-2005)
├── README.md         # This file
└── .gitignore

How It Works

When invoked, the skill follows a two-step workflow:

1. Interface Derivation — parses the user's description and displays the inferred module name, parameters, and port list
2. Code Generation + Self-Check — generates the complete module and runs a 14-point checklist

Self-Check Items

#	Check	Scope
1	File header completeness	File, Author, Date, Description, Change Log
2	File structure	resetall / timescale / default_nettype / endmodule / resetall
3	Verilog-2005 syntax	No SystemVerilog constructs
4	reg/wire driving rules	reg for always, wire for assign
5	No forward references	All signals declared before use
6	No multi-driver conflicts	One driver per signal
7	No placeholders	Complete, synthesizable implementation
8	Width matching	All assignments and port connections match widths
9	No unused signals	Every declared signal is read
10	No latch inference	Al